As the integration density of integrated circuit devices, increases, the area occupied by a unit cell continues to decrease. Since the driving capability of integrated circuit devices, such as dynamic random access memories (DRAM), is strongly dependent on the capacitance of a capacitor, a variety of attempts for increasing the capacitance of a capacitor have been carried out, irrespective of the decrease of the area occupied by the capacitor. Accordingly, in order to increase the capacitance of a capacitor by increasing the effective area of the capacitor, capacitors have been formed to have a three-dimensional structure, such as a concave shape, a cylinder shape, a fin shape, or a box shape.
Hereinafter, a method of fabricating a conventional integrated circuit memory device including a concave-shaped storage node electrode will be described with reference to FIGS. 1A through 1C. In FIGS. 1A through 1C, the drawings indicated by “X direction” are cross-sectional views of a semiconductor substrate taken along a direction parallel to word lines, and the drawings indicated by “Y direction” are cross-sectional views of a semiconductor substrate taken along a direction parallel to bit lines.
Referring to FIG. 1A, word line structures 15 are formed on a semiconductor substrate 10, on which an isolation layer 11 is formed, by a well-known method. Here, each of the word line structures 15 includes a gate insulating layer 12, a gate electrode 13 on the gate insulating layer 12, and an insulating material 14 covering the top surface and sides of the gate electrode 13. Contact plugs 16 are formed on the semiconductor substrate 10 between the word line structures 15 in a self-aligned manner, and then a first interlayer insulating layer 17 is formed on the semiconductor substrate 10 on which the contact plugs 16 are formed.
Next, a second interlayer insulating layer 18 is formed on the contact plugs 16 and the first interlayer insulating layer 17, and then is selectively etched to expose some of the contact plugs 16. Next, bit line structures 21 are formed on the second interlayer insulating layer 18, in contact with the exposed contact plugs. Here, each of the bit line structures 21 includes a bit line 19 and an insulating material 20 covering the top surface and sides of the bit line 19. A third interlayer insulating layer 22 and an etch stopper 23 are sequentially formed on the semiconductor substrate 10 on which the bit line structures 21 are formed.
Referring to FIG. 1B, predetermined portions of the etch stopper 23 and the third interlayer insulating layer 22 are etched to expose selected portions of the contact plugs 16, thereby forming storage node contact holes 24. Next, storage node contact plugs 25 are formed in the storage node contact holes 24 by a well-known method.
Next, as shown in FIG. 1C, storage node electrodes 26 are formed to be in contact with exposed storage node contact plugs 25 by a well-known method. A dielectric layer 27 is deposited along the surfaces of the storage node electrodes 26, and then a plate electrode 28 is formed on the semiconductor substrate 10 on which the dielectric layer 27 is formed.
However, the conventional integrated circuit memory device has the following problems. Firstly, as the integration density of integrated circuit memory devices increases, the pitch size of interconnections typically decreases proportionally. If the pitch size of interconnections is reduced to 0.21 Φm or less, a capacitance no less than 20 fF per a unit cell is desirable. In order to obtain capacitance having such a value, it is desirable that the height of each storage node electrode be no less than 10,000 Δ.
However, if the height of storage node electrodes is increased in order to obtain a high capacitance, the aspect ratio of a cell region can considerably increase, causing a great step difference between the cell region at which the storage node electrodes will be formed and a peripheral region at which other circuit devices will be formed. In addition, if even a slight physical impact is applied to the storage node electrodes, the storage node electrodes (capacitors) may be tilted to one side or may be broken, and thus multi-bit or twin-bit failure occurring when the upper parts of adjacent capacitors are contacted with each other may be caused.